The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2015
Filed:
Oct. 04, 2010
Harry-hak-lay Chuang, Hsinchu, TW;
Bao-ru Young, Zhubei, TW;
Kuei Shun Chen, Hsin-Chu, TW;
Cheng Cheng Kuo, Baoshun Township, Hsinchu County, TW;
George Liu, Shin-chu, TW;
Tsung-chieh Tsai, Chu-Bei, TW;
Yuhi-jier Mii, Hsin-Chu, TW;
Harry-Hak-Lay Chuang, Hsinchu, TW;
Bao-Ru Young, Zhubei, TW;
Kuei Shun Chen, Hsin-Chu, TW;
Cheng Cheng Kuo, Baoshun Township, Hsinchu County, TW;
George Liu, Shin-chu, TW;
Tsung-Chieh Tsai, Chu-Bei, TW;
Yuhi-Jier Mii, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.