The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Aug. 13, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Chieh Cheng, Hsinchu, TW;

Shih-Guei Yan, Hsinchu, TW;

Wen-Jer Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11563 (2013.01); H01L 29/792 (2013.01); H01L 29/66833 (2013.01); H01L 21/28282 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01);
Abstract

A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.


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