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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9070559 B1

PDFFull Text
Expired
Date of Patent:
Jun. 30, 2015

Filed:

Mar. 04, 2014

Pattern forming method and method of manufacturing semiconductor device

Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Seiro Miyoshi, Yokkaichi, JP;

Maki Miyazaki, Yokkaichi, JP;

Kentaro Matsunaga, Yokkaichi, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Michael Trinh

Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 21/027 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/28273 (2013.01); H01L 21/3086 (2013.01); H01L 21/0338 (2013.01); H01L 21/32139 (2013.01); H01L 21/0271 (2013.01); H01L 27/11524 (2013.01);
Abstract

According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.

Find Patent Forward Citations

Miyoshi, Seiro. (2015). Pattern forming method and method of manufacturing semiconductor device (U.S. Patent No. 9070559). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9070559

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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