The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

May. 01, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jay Madhukar Shah, Bangalore, IN;

Kamesh Medisetti, Bangalore, IN;

Vijayalakshmi Ranganna, Bangalore, IN;

Animesh Datta, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 23/5286 (2013.01);
Abstract

A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x−1 layer interconnect extending under and orthogonal to the second power rail. The x−1 layer interconnect is coupled to the set of CMOS transistor devices.


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