The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Aug. 22, 2012
Applicants:

Zhiwei Gong (Tony), Chandler, AZ (US);

Michael B Vincent, Chandler, AZ (US);

Scott M Hayes, Chandler, AZ (US);

Jason R Wright, Chandler, AZ (US);

Inventors:

Zhiwei Gong (Tony), Chandler, AZ (US);

Michael B Vincent, Chandler, AZ (US);

Scott M Hayes, Chandler, AZ (US);

Jason R Wright, Chandler, AZ (US);

Assignee:

FREESCALE SEMICONDUCTOR INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 23/49811 (2013.01); H01L 23/5389 (2013.01); H01L 25/105 (2013.01); H01L 23/3128 (2013.01); H01L 21/561 (2013.01); H01L 24/19 (2013.01); H01L 23/49805 (2013.01); H01L 21/4853 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1064 (2013.01); H01L 2924/1461 (2013.01);
Abstract

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.


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