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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9064865 B1

PDFFull Text
Expired
Date of Patent:
Jun. 23, 2015

Filed:

Oct. 11, 2013

Mechanisms for forming gate dielectric layer

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Liang-Chen Chi, Hsinchu, TW;

Chia-Ming Tsai, Zhubei, TW;

Chin-Kun Wang, Hsinchu, TW;

Jhih-Jie Huang, Taipei, TW;

Miin-Jang Chen, Taipei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

David S Blum

Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/511 (2013.01); H01L 21/28008 (2013.01);
Abstract

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.

Find Patent Forward Citations

Chi, Liang-Chen. (2015). Mechanisms for forming gate dielectric layer (U.S. Patent No. 9064865). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9064865

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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