The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Apr. 12, 2012
Applicants:

Henry Yu, Palo Alto, CA (US);

Joshua Baudhuin, Portland, OR (US);

Regis Colwell, Gibsonia, PA (US);

Harsh Deshmane, Sunnyvale, CA (US);

Elias L. Fallon, Allison Park, PA (US);

Sanjib Ghosh, Uttar Pradesh, IN;

Anjna Khanna, New Dehli, IN;

Yinnie Lee, Campbell, CA (US);

Harindranath Parameswaran, Uttar Pradesh, IN;

Pardeep Juneja, Delhi, IN;

Roland Ruehl, San Carlos, CA (US);

Simon Simonian, San Jose, CA (US);

Hui Xu, Wexford, PA (US);

Timothy Rosek, Gibsonia, PA (US);

Inventors:

Henry Yu, Palo Alto, CA (US);

Joshua Baudhuin, Portland, OR (US);

Regis Colwell, Gibsonia, PA (US);

Harsh Deshmane, Sunnyvale, CA (US);

Elias L. Fallon, Allison Park, PA (US);

Sanjib Ghosh, Uttar Pradesh, IN;

Anjna Khanna, New Dehli, IN;

Yinnie Lee, Campbell, CA (US);

Harindranath Parameswaran, Uttar Pradesh, IN;

Pardeep Juneja, Delhi, IN;

Roland Ruehl, San Carlos, CA (US);

Simon Simonian, San Jose, CA (US);

Hui Xu, Wexford, PA (US);

Timothy Rosek, Gibsonia, PA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/50 (2013.01);
Abstract

Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.


Find Patent Forward Citations

Loading…