The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Apr. 01, 2011
Applicants:

Leigang Kou, Austin, TX (US);

Jeff Wiedemeier, Austin, TX (US);

Mike Filippo, Driftwood, TX (US);

Inventors:

Leigang Kou, Austin, TX (US);

Jeff Wiedemeier, Austin, TX (US);

Mike Filippo, Driftwood, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 12/02 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 12/0215 (2013.01); G06F 9/383 (2013.01); G06F 2212/6028 (2013.01); G06F 12/0864 (2013.01); G06F 2212/6026 (2013.01);
Abstract

A method and system to optimize prefetching of cache memory lines in a processing unit. The processing unit has logic to determine whether a vector memory operand is cached in two or more adjacent cache memory lines. In one embodiment of the invention, the determination of whether the vector memory operand is cached in two or more adjacent cache memory lines is based on the size and the starting address of the vector memory operand. In one embodiment of the invention, the pre-fetching of the two or more adjacent cache memory lines that cache the vector memory operand is performed using a single instruction that uses one issue slot and one data cache memory execution slot. By doing so, it avoids additional software prefetching instructions or operations to read a single vector memory operand when the vector memory operand is cached in more than one cache memory line.


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