The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Nov. 26, 2013
Applicants:

Hyunsu Ju, Hwaseong-si, KR;

Eunmi Kim, Hwaseong-si, KR;

Yoocheol Shin, Hwaseong-si, KR;

Min Kyu Yang, Hwaseong-si, KR;

Jungdal Choi, Hwaseong-si, KR;

Inventors:

Hyunsu Ju, Hwaseong-si, KR;

Eunmi Kim, Hwaseong-si, KR;

Yoocheol Shin, Hwaseong-si, KR;

Min Kyu Yang, Hwaseong-si, KR;

Jungdal Choi, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 27/2454 (2013.01); H01L 27/2481 (2013.01);
Abstract

Resistive memory devices are provided having a gate stack including insulating layers and gates stacked on a substrate in a vertical direction, a channel penetrating the gate stack in the vertical direction to be electrically connected to the substrate, a gate insulating layer provided between the channel and the gates, and a variable resistance layer disposed along an extending direction of the channel. The gate stack may include an alcove formed by recessing the gate in a horizontal direction. The variable resistance layer may extend toward the alcove in the horizontal direction and be overlapped with at least one of the gates in the horizontal direction. Related methods are also provided.


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