The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Aug. 02, 2012
Applicants:

Emre Alptekin, Wappingers Falls, NY (US);

Gregory Allen Northrop, Putnam Valley, NY (US);

Viraj Yashawant Sardesai, Poughkeepsie, NY (US);

Cung DO Tran, Newburgh, NY (US);

Inventors:

Emre Alptekin, Wappingers Falls, NY (US);

Gregory Allen Northrop, Putnam Valley, NY (US);

Viraj Yashawant Sardesai, Poughkeepsie, NY (US);

Cung Do Tran, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/823828 (2013.01); H01L 27/088 (2013.01); H01L 21/823437 (2013.01); H01L 29/49 (2013.01); H01L 29/66545 (2013.01);
Abstract

Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.


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