Semiconductor-on-insulator (soi) structure with selectivity placed sub-insulator layer void(s) and method of forming the soi structure

Abstract

Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.