The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Dec. 04, 2013
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

David A. Kewley, Boise, ID (US);

Brian Cleereman, Boise, ID (US);

Stephen W. Russell, Boise, ID (US);

Rex Stone, Albuquerque, NM (US);

Anthony C. Krauth, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32133 (2013.01); H01L 21/0337 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/32139 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11568 (2013.01); H01L 21/28008 (2013.01);
Abstract

Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.


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