The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Mar. 04, 2010
Applicants:

Jean R. Vatus, San Jose, CA (US);

Jinsong Tang, Livermore, CA (US);

Yihwan Kim, Milpitas, CA (US);

Satheesh Kuppurao, San Jose, CA (US);

Errol Sanchez, Tracy, CA (US);

Inventors:

Jean R. Vatus, San Jose, CA (US);

Jinsong Tang, Livermore, CA (US);

Yihwan Kim, Milpitas, CA (US);

Satheesh Kuppurao, San Jose, CA (US);

Errol Sanchez, Tracy, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); C23C 16/02 (2006.01); C23C 16/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02538 (2013.01); C23C 16/0245 (2013.01); C23C 16/24 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02661 (2013.01);
Abstract

Methods of depositing layers having reduced interfacial contamination are disclosed herein. The inventive methods may advantageously reduce contamination at the interface between deposited layers, for example, between a deposited layer and an underlying substrate or film. In some embodiments, a method of depositing a layer may include annealing a silicon-containing layer having a first layer disposed thereon in a reducing atmosphere; removing the first layer using an etching process to expose the silicon-containing layer after annealing; and depositing a second layer on the exposed silicon-containing layer.


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