The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Aug. 28, 2013
Synopsys, Inc., Mountain View, CA (US);
Tao Lin, Palo Alto, CA (US);
Jieyi Long, San Jose, CA (US);
Anand Rajaram, Austin, TX (US);
Michael Bezman, Sunnyvale, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the graph. To apply linear programming to the graph, the method generates a set of constraints for the graph and determines a proper insertion delay for each edge of the graph by solving for a minimal skew based on the set of constraints. The method implements the optimal clock network balancing solution.