The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Dec. 15, 2009
Applicant:

Abhijeet Kolpekwar, Round Rock, TX (US);

Inventor:

Abhijeet Kolpekwar, Round Rock, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06G 7/62 (2006.01); G06G 7/54 (2006.01);
U.S. Cl.
CPC ...
G06F 17/50 (2013.01); G06F 17/5036 (2013.01); G06F 17/5045 (2013.01); G06F 17/5009 (2013.01);
Abstract

Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.


Find Patent Forward Citations

Kolpekwar, Abhijeet. (2015). Method and mechanism for verifying and simulating power aware mixed-signal electronic designs (U.S. Patent No. 9058440). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9058440

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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