The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Dec. 16, 2011
Applicants:

Kerry Nagel, Phoenix, AZ (US);

Kenneth Smith, Chandler, AZ (US);

Moazzem Hossain, Laveen, AZ (US);

Sanjeev Aggarwal, Scottsdale, AZ (US);

Inventors:

Kerry Nagel, Phoenix, AZ (US);

Kenneth Smith, Chandler, AZ (US);

Moazzem Hossain, Laveen, AZ (US);

Sanjeev Aggarwal, Scottsdale, AZ (US);

Assignee:

Everspin Technologies, Inc., Chandler, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 27/222 (2013.01); H01L 43/08 (2013.01); H01L 21/76819 (2013.01); H01L 21/76877 (2013.01); H01L 27/228 (2013.01);
Abstract

A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F, and a uniform thickness of material between the bit lines and the underlying memory elements.


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