The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jun. 28, 2012
Applicants:

Ankush Varma, Hillsboro, OR (US);

Buck W. Gremel, Olympia, WA (US);

Robert G. Blankenship, Tacoma, WA (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

Michael F. Cole, Folsom, CA (US);

Inventors:

Ankush Varma, Hillsboro, OR (US);

Buck W. Gremel, Olympia, WA (US);

Robert G. Blankenship, Tacoma, WA (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

Michael F. Cole, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4018 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01); G06F 1/3203 (2013.01);
Abstract

Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.


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