The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Jul. 01, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Tong-Yu Chen, Hsinchu, TW;

Kuo-Yuh Yang, Hsinchu County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 21/76898 (2013.01); H01L 21/7624 (2013.01);
Abstract

A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.


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