The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Jun. 16, 2011
Applicants:

Akio Horiuchi, Nagano, JP;

Toshiji Miyasaka, Nagano, JP;

Inventors:

Akio Horiuchi, Nagano, JP;

Toshiji Miyasaka, Nagano, JP;

Assignee:

SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano-shi, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 24/97 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/16 (2013.01); H01L 2224/20 (2013.01); H01L 2224/211 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15165 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/16195 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/97 (2013.01);
Abstract

In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.


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