The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Apr. 22, 2014
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Moshe Agam, Portland, OR (US);

Thierry Coffi Herve Yao, Portland, OR (US);

Skip Shizhen Liu, Lake Oswego, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/525 (2006.01); H01L 27/112 (2006.01); H01L 27/10 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5252 (2013.01); H01L 27/11206 (2013.01); H01L 27/101 (2013.01); H01L 29/78 (2013.01);
Abstract

An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.


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