The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Jan. 03, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ilango S. Ganga, Cupertino, CA (US);
Luke Chang, Aloha, OR (US);
Andrey Belogolovy, Saint-Petersburg, RU;
Andrei Ovchinnikov, Saint-Petersburg, RU;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); H03M 13/33 (2006.01); H04L 1/00 (2006.01); H04L 7/04 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
G06F 11/10 (2013.01); H03M 13/33 (2013.01); H03M 13/63 (2013.01); H04L 1/0041 (2013.01); H04L 1/0047 (2013.01); H04L 1/0057 (2013.01); H04L 1/0072 (2013.01); H04L 7/033 (2013.01); H04L 7/041 (2013.01); Y02B 60/44 (2013.01);
Abstract
Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.