The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Sep. 29, 2012
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Zhen Fang, Portland, OR (US);
Shih-Lien Lu, Portland, OR (US);
Ravishankar Iyer, Portland, OR (US);
Srihari Makineni, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, unknown;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/00 (2006.01); G06F 1/32 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/004 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G11C 5/14 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1285 (2013.01);
Abstract
Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.