The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Nov. 08, 2007
Applicants:

Guy Shafran, Rosh-Pina, IL;

Oded Bashan, Rosh-Pina, IL;

Inventors:

Guy Shafran, Rosh-Pina, IL;

Oded Bashan, Rosh-Pina, IL;

Assignee:

SMARTRAC IP B.V., Amsterdam, NL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 19/077 (2006.01);
U.S. Cl.
CPC ...
G06K 19/07745 (2013.01); Y10T 29/53178 (2015.01); Y10T 29/49016 (2015.01); Y10T 29/49117 (2015.01); Y10T 29/4913 (2015.01); Y10T 29/5317 (2015.01); Y10T 29/49002 (2015.01); Y10T 29/49169 (2015.01); Y10T 29/49018 (2015.01); G06K 19/07749 (2013.01); G06K 19/0775 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for manufacture of an electronic interface card () including defining a pair of apertures in a substrate layer (), associating an antenna () with the substrate layer () such that opposite ends of the antenna () terminate at the apertures, placing a metal element in each of the apertures, connecting the ends of the antenna to the metal elements, laminating the substrate layer together with a top layer () and a bottom layer (), forming a recess () in the top layer and the substrate layer, attaching end of connection wires () to the metal elements, attaching opposite ends of the connection wires () to a chip module () and sealing the chip module in the recess ().


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