The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Jun. 29, 2012
Ankush Varma, Hillsboro, OR (US);
Krishnakanth V. Sistla, Beaverton, OR (US);
Martin T. Rowland, Beaverton, OR (US);
Chris Poirier, Fort Collins, CO (US);
Eric J. Dehaemer, Shrewsbury, MA (US);
Avinash N. Ananthakrishnan, Hillsboro, OR (US);
Jeremy J. Shrall, Portland, OR (US);
Xiuting C. Man, Portland, OR (US);
Stephen H. Gunther, Portland, OR (US);
Krishna K. Rangan, Hudson, MA (US);
Devadatta V. Bodas, Federal Way, WA (US);
Don Soltis, Windsor, CO (US);
Hang T. Nguyen, Tempe, AZ (US);
Cyprian W. Woo, Blaine, WA (US);
Thi Dang, Olympia, WA (US);
Ankush Varma, Hillsboro, OR (US);
Krishnakanth V. Sistla, Beaverton, OR (US);
Martin T. Rowland, Beaverton, OR (US);
Chris Poirier, Fort Collins, CO (US);
Eric J. Dehaemer, Shrewsbury, MA (US);
Avinash N. Ananthakrishnan, Hillsboro, OR (US);
Jeremy J. Shrall, Portland, OR (US);
Xiuting C. Man, Portland, OR (US);
Stephen H. Gunther, Portland, OR (US);
Krishna K. Rangan, Hudson, MA (US);
Devadatta V. Bodas, Federal Way, WA (US);
Don Soltis, Windsor, CO (US);
Hang T. Nguyen, Tempe, AZ (US);
Cyprian W. Woo, Blaine, WA (US);
Thi Dang, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.