The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Aug. 20, 2009
Applicants:

Akihiro Matsuse, Nagoya, JP;

Kotaro Yano, Kawasaki, JP;

Inventors:

Akihiro Matsuse, Nagoya, JP;

Kotaro Yano, Kawasaki, JP;

Assignee:

SHOWA DENKO K.K., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 21/28 (2006.01); H01L 21/04 (2006.01); H01L 29/45 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01); H01L 29/872 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0485 (2013.01); H01L 21/0495 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01); H01L 29/6606 (2013.01); H01L 29/872 (2013.01);
Abstract

There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer. Such a semiconductor device includes an n type SiC semiconductor substrate (), a cathode electrode () that comes into ohmic contact with a main surface () of one side of the SiC semiconductor substrate (), a first semiconductor region () that is made of p type SiC formed in a main surface () of the other side of the SiC semiconductor substrate (), a second semiconductor region () that is made of an n type SiC formed in the main surface () of the other side, an ohmic junction layer () that comes into ohmic contact with the first semiconductor region (), and a Schottky junction layer () that comes into Schottky contact with the second semiconductor region (), wherein a root mean square roughness for a surface of the ohmic junction layer () is 20 nm or less.


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