The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Dec. 19, 2011
Applicants:

Wei-chih Chien, Taipei, TW;

Ming-hsiu Lee, Hsinchu, TW;

Shih-hung Chen, Hsinchu, TW;

Inventors:

Wei-Chih Chien, Taipei, TW;

Ming-Hsiu Lee, Hsinchu, TW;

Shih-Hung Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2409 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/1633 (2013.01); H01L 27/249 (2013.01);
Abstract

A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.


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