The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Mar. 29, 2007
Applicants:

Yao-tsung Huang, Kaohsiung County, TW;

Chien-ting Lin, Hsinchu, TW;

Che-hua Hsu, Hsinchu County, TW;

Guang-hwa MA, Hsinchu, TW;

Inventors:

Yao-Tsung Huang, Kaohsiung County, TW;

Chien-Ting Lin, Hsinchu, TW;

Che-Hua Hsu, Hsinchu County, TW;

Guang-Hwa Ma, Hsinchu, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
C30B 1/02 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01); C30B 29/06 (2006.01); C30B 33/00 (2006.01); H01L 21/265 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/045 (2013.01); H01L 21/02532 (2013.01); H01L 21/02609 (2013.01); C30B 1/023 (2013.01); C30B 29/06 (2013.01); C30B 33/00 (2013.01); H01L 21/26506 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 29/7847 (2013.01);
Abstract

A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.


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