The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Jul. 16, 2013
Applicants:

Chen He, Austin, TX (US);

Yanzhuo Wang, Austin, TX (US);

Fuchen Mu, Austin, TX (US);

Inventors:

Chen He, Austin, TX (US);

Yanzhuo Wang, Austin, TX (US);

Fuchen Mu, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01);
Abstract

Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.


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