The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2015
Filed:
Dec. 12, 2011
Applicants:
Roy E. Scheuerlein, Cupertino, CA (US);
Raul-adrian Cernea, Santa Clara, CA (US);
Inventors:
Roy E. Scheuerlein, Cupertino, CA (US);
Raul-Adrian Cernea, Santa Clara, CA (US);
Assignee:
SanDisk 3D LLC, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 45/00 (2006.01); H01L 27/115 (2006.01); H01L 27/06 (2006.01); H01L 27/24 (2006.01); G11C 8/08 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); H01L 27/115 (2013.01); H01L 27/0688 (2013.01); H01L 27/2481 (2013.01); H01L 27/2463 (2013.01); G11C 8/08 (2013.01); G11C 13/0002 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01); H01L 27/2454 (2013.01); H01L 27/249 (2013.01); G11C 13/0028 (2013.01); H01L 45/165 (2013.01); H01L 45/1683 (2013.01); G11C 13/0026 (2013.01); G11C 5/025 (2013.01);
Abstract
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.