The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Dec. 14, 2010
Applicants:

Thorsten Meyer, Regensburg, DE;

Ludwig Heitzer, Falkenfels, DE;

Inventors:

Thorsten Meyer, Regensburg, DE;

Ludwig Heitzer, Falkenfels, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 24/02 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/02379 (2013.01); H01L 24/13 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2924/01322 (2013.01); H01L 2224/02311 (2013.01); H01L 2924/01029 (2013.01);
Abstract

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.


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