The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Jun. 14, 2013
Applicants:

Poh Leng Eu, Petaling Jaya, MY;

Boon Yew Low, Petaling Jaya, MY;

Kai Yun Yow, Petaling Jaya, MY;

Inventors:

Poh Leng Eu, Petaling Jaya, MY;

Boon Yew Low, Petaling Jaya, MY;

Kai Yun Yow, Petaling Jaya, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 21/565 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/97 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01);
Abstract

A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.


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