Reverse interface logic model for optimizing physical hierarchy under full chip constraint

Abstract

A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors. Conventional design bottlenecks may be bypassed for greatly improved quality of results and reduced turnaround time.