The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Mar. 29, 2012
Applicants:

Rajen S. Sidhu, Chandler, AZ (US);

Ashay A. Dani, Chandler, AZ (US);

Martha A. Dudek, Chandler, AZ (US);

Inventors:

Rajen S. Sidhu, Chandler, AZ (US);

Ashay A. Dani, Chandler, AZ (US);

Martha A. Dudek, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53209 (2013.01); H01L 2224/1308 (2013.01); H01L 2224/11005 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/1132 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/11901 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/14505 (2013.01); H01L 2224/16507 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/8181 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/3511 (2013.01); H01L 21/76882 (2013.01);
Abstract

Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.


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