The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Apr. 26, 2010
Applicants:

Akira Muto, Kanagawa, JP;

Yuichi Machida, Tokyo, JP;

Nobuya Koike, Kanagawa, JP;

Atsushi Fujiki, Kanagawa, JP;

Masaki Tamura, Kanagawa, JP;

Inventors:

Akira Muto, Kanagawa, JP;

Yuichi Machida, Tokyo, JP;

Nobuya Koike, Kanagawa, JP;

Atsushi Fujiki, Kanagawa, JP;

Masaki Tamura, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/07 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/074 (2013.01); H01L 23/49537 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 21/565 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/13091 (2013.01); H01L 2224/33181 (2013.01); H01L 23/3107 (2013.01);
Abstract

A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.


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