The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Mar. 13, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hongjun Yao, San Diego, CA (US);

Michael Laisne, Encinitas, CA (US);

Matthew M Nowak, San Diego, CA (US);

Glen T Kim, San Diego, CA (US);

Mark C Chan, San Diego, CA (US);

Shiqun Gu, San Diego, CA (US);

Assignee:

QUALCOMM, Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 22/14 (2013.01); H01L 2924/0002 (2013.01); H01L 2224/16 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.


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