The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

May. 22, 2012
Applicants:

Jin Yong an, Daejeon, KR;

Jae Joon Lee, Gyunggi-do, KR;

Inventors:

Jin Yong An, Daejeon, KR;

Jae Joon Lee, Gyunggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 3/40 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 3/46 (2006.01); H05K 3/10 (2006.01); H05K 3/20 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4007 (2013.01); H01L 21/4857 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 2221/68345 (2013.01); H05K 3/108 (2013.01); H05K 3/205 (2013.01); H05K 3/4682 (2013.01); H05K 2201/0367 (2013.01); H05K 2203/0228 (2013.01); H05K 2203/0376 (2013.01); H05K 2203/054 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of manufacturing a printed circuit board, including: applying a dry film on a carrier and then patterning the dry film to form holes for forming metal bumps; forming an upper circuit layer including metal bumps charged in the holes and connection pads on the dry film; forming an insulation layer on the dry film; forming a build-up layer including a lower circuit layer on the insulation layer; removing the carrier; and removing the dry film.


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