The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9018995 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 28, 2015

Filed:

Dec. 03, 2009
Applicants:

Kumar Subramani, Redwood City, CA (US);

Radu Zlatanovici, Oakland, CA (US);

Inventors:

Kumar Subramani, Redwood City, CA (US);

Radu Zlatanovici, Oakland, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/356 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356156 (2013.01); H03K 3/012 (2013.01);
Abstract

A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.


Find Patent Forward Citations

Subramani, Kumar. (2015). Integrated clock gating cell for circuits with double edge triggered flip-flops (U.S. Patent No. 9018995). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9018995

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