The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Mar. 05, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Guei Yan, Hsinchu, TW;

Wen-Jer Tsai, Hsinchu, TW;

Cheng-Hsien Cheng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 29/42332 (2013.01); H01L 29/42348 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H01L 27/11521 (2013.01); H01L 27/11568 (2013.01);
Abstract

A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.


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