The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Mar. 15, 2013
Applicants:

Stmicroelectronics International N.v., Amsterdamn, NL;

Stmicroelectronics S.r.l, Agrate Brianza, IT;

Inventors:

Joshipura Jwalant, Noida, IN;

Nitin Bansal, Gurgaon, IN;

Amit Katyal, Ghaziabad, IN;

Massimiliano Picca, Muggio, IT;

Assignees:

STMicroelectronics International N.V., Amsterdam, NL;

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H05K 3/30 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H05K 3/30 (2013.01); G06F 17/5063 (2013.01);
Abstract

An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.


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