The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Oct. 01, 2011
Applicants:

Keith A. Jones, DuPont, WA (US);

Daniel R. Pfunder, Noblesville, IN (US);

John H. Zurawski, Boxborough, MA (US);

Inventors:

Keith A. Jones, DuPont, WA (US);

Daniel R. Pfunder, Noblesville, IN (US);

John H. Zurawski, Boxborough, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/319 (2006.01); G06F 11/267 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/318547 (2013.01); G01R 31/31908 (2013.01); G06F 11/267 (2013.01);
Abstract

Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing. This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface. The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports.


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