The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2015
Filed:
May. 05, 2014
Diablo Technologies Inc., Ottawa, CA;
Maher Amer, Nepean, CA;
Michael Lewis Takefman, Nepean, CA;
Diablo Technologies, Inc., Ottawa, CA;
Abstract
A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).