The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Mar. 18, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Yasuhiro Nojiri, Yokohama, JP;

Shigeki Kobayashi, Kuwana, JP;

Masaki Yamato, Yokkaichi, JP;

Hiroyuki Fukumizu, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4193 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0002 (2013.01);
Abstract

A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.


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