The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Dec. 10, 2013
Applicant:

Ememory Technology Inc., Hsinchu, TW;

Inventors:

Chin-Yi Chen, New Taipei, TW;

Lun-Chun Chen, Yilan County, TW;

Yueh-Chia Wen, Taoyuan County, TW;

Meng-Yi Wu, Hsinchu County, TW;

Hsin-Ming Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01); G11C 17/16 (2006.01); H01L 27/112 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
G11C 17/16 (2013.01); H01L 27/11206 (2013.01); H01L 23/5252 (2013.01); G11C 17/18 (2013.01);
Abstract

Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.


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