The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Nov. 21, 2012
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Ren Chen, Zhudong Township, TW;

Guang-Cheng Wang, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 9/04 (2006.01); H01C 7/12 (2006.01); H02H 1/00 (2006.01); H02H 1/04 (2006.01); H02H 3/22 (2006.01); H02H 9/06 (2006.01);
U.S. Cl.
CPC ...
H02H 9/041 (2013.01);
Abstract

A multiple device voltage electrostatic discharge (ESD) clamp includes a trigger circuit, first and second inverters, and an ESD discharge path. The trigger circuit includes a resistor having a first terminal electrically connected to a first voltage supply node, and a capacitor having a first terminal electrically connected to a second voltage supply node. The first inverter has an input terminal electrically connected to second terminals of the resistor and the capacitor. The second inverter has a power terminal electrically connected to an output terminal of the first inverter. The ESD discharge path has a first end electrically connected to the first voltage supply node, and a second end electrically connected to a third voltage supply node, and includes a first transistor controlled by the first inverter, and a second transistor controlled by the second inverter.


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