The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Dec. 27, 2012
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Jui Liang, Tainan, TW;

Po-Chao Tsao, New Taipei, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 27/088 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 21/823468 (2013.01);
Abstract

A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.


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