The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Apr. 18, 2013
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Digh Hisamoto, Kokubunji, JP;

Shinichiro Kimura, Kunitachi, JP;

Kan Yasui, Kodaira, JP;

Nozomu Matsuzaki, Kokubunji, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 21/28282 (2013.01); H01L 27/115 (2013.01); H01L 27/11568 (2013.01); H01L 29/792 (2013.01);
Abstract

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.


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