The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Oct. 24, 2011
Applicants:

Lars Samuelson, Malmö, SE;

Jonas Ohlsson, Malmö, SE;

Thomas Mårtensson, Lund, SE;

Patrik Svensson, Palo Alto, CA (US);

Inventors:

Lars Samuelson, Malmö, SE;

Jonas Ohlsson, Malmö, SE;

Thomas Mårtensson, Lund, SE;

Patrik Svensson, Palo Alto, CA (US);

Assignee:

Qunano AB, Lund, SE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 31/00 (2006.01); B81C 1/00 (2006.01); B82Y 10/00 (2011.01); H01L 21/02 (2006.01); H01L 33/18 (2010.01);
U.S. Cl.
CPC ...
H01L 29/0665 (2013.01); B81C 1/00111 (2013.01); B82Y 10/00 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02538 (2013.01); H01L 21/02609 (2013.01); H01L 21/02645 (2013.01); H01L 21/02653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/068 (2013.01); H01L 33/18 (2013.01); Y10S 977/89 (2013.01); Y10S 977/762 (2013.01); Y10S 977/949 (2013.01); Y10S 438/974 (2013.01); Y10S 977/721 (2013.01); Y10S 977/815 (2013.01); Y10S 438/946 (2013.01);
Abstract

The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.


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