The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Feb. 27, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Hajime Eda, Kanagawa-ken, JP;

Gaku Minamihaba, Kanagawa-ken, JP;

Yukiteru Matsui, Aichi-ken, JP;

Akifumi Gawase, Mie-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); B24B 49/02 (2006.01); B24B 37/013 (2012.01); B24B 49/10 (2006.01); H01L 21/768 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); B24B 49/02 (2013.01); B24B 37/013 (2013.01); B24B 49/105 (2013.01); H01L 22/26 (2013.01); H01L 21/7684 (2013.01); H01L 21/3212 (2013.01);
Abstract

According to an embodiment, a method of manufacturing a semiconductor device includes forming a wiring groove on an insulating film; forming a barrier metal layer and a metal layer; polishing the metal layer by applying a first load on the metal layer; and subsequently polishing the metal layer while applying a second load larger than the first load on the metal layer and spraying a gas onto a polishing pad. The polishing pad is in contact with the metal layer. The barrier metal layer covers an upper surface of the insulating film and an inner surface of the wiring groove, and the metal layer fills an inside of the wiring groove and covers the barrier metal layer.


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