The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Dec. 05, 2012
Applicants:

Christopher P. Mozak, Beaverton, OR (US);

Theodore Z. Schoenborn, Portland, OR (US);

James M. Shehadi, Portland, OR (US);

David G. Ellis, Tualatin, OR (US);

Tomer Levy, Tel Aviv, IL;

Zvika Greenfield, Kfar Sava, IL;

Inventors:

Christopher P. Mozak, Beaverton, OR (US);

Theodore Z. Schoenborn, Portland, OR (US);

James M. Shehadi, Portland, OR (US);

David G. Ellis, Tualatin, OR (US);

Tomer Levy, Tel Aviv, IL;

Zvika Greenfield, Kfar Sava, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/263 (2006.01); G11C 29/02 (2006.01); G11C 29/06 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/263 (2013.01); G11C 29/02 (2013.01); G11C 29/025 (2013.01); G11C 29/06 (2013.01); G11C 29/52 (2013.01);
Abstract

A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.


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