The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Oct. 18, 2012
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chad A. Adams, Byron, MN (US);

Sharon H. Cesky, Rochester, MN (US);

Elizabeth L. Gerhard, Rochester, MN (US);

Jeffrey M. Scherer, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 11/413 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01);
Abstract

An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.


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